A programmable logic device, such as a field programmable gate array (FPGA), contains logic resources, which can be programmed to perform particular functions, so that the device has an intended functionality. In a purely programmable device, there may be no differentiation between the logic resources, and then every desired function must be implemented using these generic resources.
However, the operation of the programmed device may be more efficient if the device is able to use resources which have a particular dedicated function. That is, if some of the logic resources of the device have a dedicated function, then that function can probably be carried out more efficiently using those resources. As a result, programmable logic devices commonly contain some logic resources which can be programmed to perform a wide range of functions, plus some resources which are optimised for performing specific functions.
For example, the Stratix® II FPGA, available from Altera Corporation, contains some logic resources, which are optimised for particular functions. Since programmable logic devices commonly have to perform arithmetic functions on input data, particularly if they are used in signal processing applications, for example, the Stratix® II FPGA contains logic resources, which are optimised for performing addition.
Programmable logic devices are also commonly used to implement multiplexers, since multiplexers are often used in a wide range of functions.
In particular, there are two types of multiplexer, which are commonly implemented. Firstly, there is a priority multiplexer, in which there are multiple select input signals, and multiple data signals. The select input signals have a priority ordering. For example, in the case of a priority multiplexer having two select input signals and three data signals, if the higher priority select input signal has a first binary value (for purposes of illustration, this can be taken to be the value “1”, but this is not necessarily the case), then a first data signal is supplied to the output, irrespective of the value of the lower priority select input signal. However, if the higher priority select input signal has a second binary value (that is, the value “0” if the first binary value is taken to be the value “1”), then either the second or third data signal is supplied to the output, depending on the value of the lower priority select input signal.
Secondly, there is a “one hot” multiplexer, in which there are the same numbers of select input signals and data signals. At any time, only one of the select input signals has a first binary value (for purposes of illustration, this can again be taken to be the value “1”, but this is not necessarily the case), which causes the corresponding data signal to be supplied to the output.
In practice, if a “one hot” multiplexer function is required, then this can be implemented using a priority multiplexer, provided that it is ensured that only one of the select input signals of the priority multiplexer has the first binary value at any time.
However, conventional “one hot” multiplexers are faster than priority multiplexers, and so “one hot” multiplexers are implemented where possible, when the functionality of a “one hot” multiplexer is required. Nevertheless, all multiplexers introduce significant delays in the operation of designs implemented in an FPGA, thereby limiting the speed at which the design can operate.